1. Field of the Invention
The present invention relates to a memory system and a bus switch.
2. Description of the Related Art
Solid state drive (SSD) has recently attracted attention as a memory system equipped with a flash memory (flash EEPROM), as an external memory used for a computer system. The flash memory has advantages such as high speed and lightweight, as compared to a magnetic disk unit.
An SSD includes a plurality of flash memory chips, a controller that controls reading and writing of the respective flash memory chips in response to a request from a host device, a buffer memory for performing data transfer between the respective flash memory chips and the host device, a power circuit, and a connection interface with respect to the host device (for example, Japanese Patent Publication No. 3688835).
When an SSD is designed, however, a stacked product in which a plurality of memory chips is stacked needs to be used to increase a data capacity, while the number of pins of a controller chip and mounting footprints are limited. In such a stacked product, an IO signal line and a control signal line are arranged for several memory chips inside thereof, and a load capacity of respective signal lines increases with an increase of the stacked number of memory chips.
When the load capacity of the respective signal lines increases, a delay occurs due to a CR delay in the IO signal and the control signal. When a synchronously designed controller is used, data read from a memory can be latched and output in a low load state (with the number of stacks being small); however, in a high load state (with the number of stacks being large), the data read from the memory may not be latched and output due to a delay in the data caused by the CR delay.
Likewise, when the load capacity of each signal lines increases, a write error may occur with respect to the memory due to a signal delay.